Tech Xplore on MSN

Tiny silicon structures compute with heat, achieving 99% accurate matrix multiplication

MIT researchers have designed silicon structures that can perform calculations in an electronic device using excess heat ...
Le Lézard

MicroCloud Hologram Inc. Utilizes FPGA to Accelerate Tensor Network Computing to Achieve Quantum Spin Models

MicroCloud Hologram Inc. , ("HOLO" or the "Company"), a technology service provider, proposed an innovative hardware acceleration technology that converts the quantum tensor network algorithm into ...
Morning Overview on MSN

MIT’s heat-powered silicon chips hit 99% accuracy in math tests

Engineers at MIT have turned one of computing’s biggest headaches, waste heat, into the main act. By sculpting “dust-sized” silicon structures that steer heat as precisely as electrical current, they ...
Nanowerk

Stacked memristor arrays compute Euclidean distance in memory to accelerate self-organizing maps

A novel stacked memristor architecture performs Euclidean distance calculations directly within memory, enabling ...
New Electronics

Taking the axe to AI

“We must strive for better,” said IBM Research chief scientist Ruchir Puri at a conference on AI acceleration organised by the computer company and the IEEE in November. He expects almost all language ...
IEEE

ScanNow: A Scan Window-Based Sparse Matrix Multiplication Accelerator Design

Sparse matrix-matrix multiplication (SpMM) is a crucial kernel in various applications, including sparse deep neural networks [1]–[6], graph analytics [7], triangle counting [8], and linear algebra ...
IEEE

MH-SpGEMM: Efficient Sparse General Matrix-Matrix Multiplication on Modern GPUs via Masking and Hashing Cooperative Optimization

Abstract: Sparse General Matrix-Matrix Multiplication (SpGEMM) is a core operation in high-performance computing applications such as algebraic multigrid solvers, machine learning, and graph ...